yosys: Open Synthesis suite¹

Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains

... part of T2, get it here

URL: https://yosyshq.net/yosys/

Author: Claire Xenia Wolf <claire [at] clairexen [dot] net>
Maintainer: Rene Rebe <rene [at] t2-project [dot] org>

License: ISC
Status: Beta
Version: 0.60

Download: https://github.com/YosysHQ/yosys/ yosys.tar.gz

T2 source: yosys.cache
T2 source: yosys.desc
T2 source: yosys.prof

Build time (on reference hardware): 1850% (relative to binutils)²

Installed size (on reference hardware): 47.64 MB, 329 files

Dependencies (build time detected): bash bison clang coreutils cxxheaderparser diffutils flex gawk gettext git grep gzip libffi linux-header m4 make openssl pkgconfig pybind python python-gpep517 sed setuptools tar tcl zlib

Installed files (on reference hardware): [show]

¹) This page was automatically generated from the T2 package source. Corrections, such as dead links, URL changes or typos need to be performed directly on that source.

²) Compatible with Linux From Scratch's "Standard Build Unit" (SBU).